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Towards a generic programming model for network processors

Lee, K., Coulson, G., Blair, G., Joolia, A. and Ueyama, J. (2004) Towards a generic programming model for network processors. In: IEEE 12th International Conference on Networks (ICON 04), 16 - 19 November, Singapore pp. 504-510.

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Network processors (NPs) are emerging as a cost effective network element technology that can be more readily updated and evolved than custom hardware or ASIC-based designs. Moreover, NPs promise support for run-time reconfiguration of low-level networking software. However, it is notoriously difficult to develop software for NPs because of their complex design, architectural heterogeneity, and demanding performance constraints. In this paper we present a runtime component-based approach to programming NPs. The approach promotes conceptual uniformity and design portability across a wide variety of NP types while simultaneously exploiting hardware assists that are specific to individual NPs. To show how our approach can be applied in a wide range of types of NPs we characterise the design space of NPs and demonstrate the applicability of our concepts to the various classes identified. Then, as a detailed case study, we focus on programming the Intel IXP1200 NP. This demonstrates that our approach can be effectively applied, e.g. in terms of performance, in a demanding real-world NP environment.

Item Type: Conference Paper
Publisher: IEEE
Copyright: © 2004 IEEE
Notes: Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Appears in Proceedings of the IEEE 12th International Conference on Networks (ICON 04), pp 504 - 510.
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