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Design and analysis of using a programmable network interface for high speed networks beyond the 10 Gbps

Elbeshti, M., Dixon, M. and Koziniec, T. (2011) Design and analysis of using a programmable network interface for high speed networks beyond the 10 Gbps. Journal of Computer Science and Engineering, 7 (2). pp. 31-42.

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Abstract

The networks speed has been advancing rapidly in providing higher transmission rate 10 Gbps and over. These improvements based on the demand of enhancing the network services, improving their bandwidth and integrating advanced technology. As the speed of networks exceeds 10 Gbps, the design and implementation of high-performance Network Interfaces (NI) for the current and the Next Generation Network (NGN) server applications that employ TCP/IP and UDP/IP as the communication protocol of choice is becoming very challenging. Using the General Purpose Processor (GPP) as a main core processor in the NI to offload the TCP/IP or UDP/IP functions, can deliver some important features to NI such as scalability and short developing time. However, it is not clear that using GPP can support the new speed line over the 10 Gbps. Furthermore, it is necessary to find out the clock rate Hz limit of these GPP in supporting the processing of NIs. In this research, we have proposed a new programmable Ethernet NI (ENI) model design to support the high speed transmission. This model supports the Large Segment Offload (LSO) for sending side and a novel algorithm for receiving side called Receiving Side Amalgamating Algorithm (RSAA). As a result, a 240 MHz RISC core can be used in this Ethernet NI card for a wide range of the transmission line speeds up to 100 Gbps when a jumbo packet assigned as a default size for a network.

Publication Type: Journal Article
Murdoch Affiliation: School of Information Technology
Copyright: © 2011 JCSE
URI: http://researchrepository.murdoch.edu.au/id/eprint/6571
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