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A study using a RISC core for 100 GBPS Ethernet Network Interfaces

Elbeshti, M. and Dixon, M. (2011) A study using a RISC core for 100 GBPS Ethernet Network Interfaces. Advanced Materials Research, 403-40 . pp. 522-531.

Link to Published Version: http://dx.doi.org/10.4028/www.scientific.net/AMR.4...
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Abstract

The performance of the current and the next generation server applications such as ECommerce, Storage and Web server that employ TCP/IP and UDP/IP as the communication protocol of choice depends upon the efficiency of the Protocol Stack Processing within this node. As the speed of networks exceeds one GBPS, the design and implementation of high-performance Network Interfaces (NI) for servers become very challenging. It is observed that using programmable NI with a general purpose processing core to offload some of the TCP/IP or UDP/IP protocol functions can deliver some important features which include scalability, short development times and reduced costs. In this paper, we proposes a new NI-programmable based model that support the Large Segment Offload (LSO) for sending side and a novel technique called Receiving Side Amalgamating (RSA) for receiving side and which is used for incoming packets. The core engine assigned to handle these functions is single specialized embedded processors utilizing RISC cores in each side. As a result, a 240 MHz RISC core can be used in Ethernet Network Interface ENI card for wide range of transmission line speed up to 100 Gbps. These results are based on the use of a specialized RISC core that we developed and simulated. Also, the author has discussed some of the design issues that are related to RISC core based NI and the data movement type.

Publication Type: Journal Article
Murdoch Affiliation: School of Information Technology
Publisher: trans tech publications
Copyright: © (2012) Trans Tech Publications
URI: http://researchrepository.murdoch.edu.au/id/eprint/6400
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